The present disclosure relates to a carbon nanotube device, and particularly to a carbon nanotube transistor employing carbon nanotubes self-aligned to embedded electrodes and methods of manufacturing the same.
Semiconducting carbon nanotubes are direct bandgap semiconductors and have potential as channel material in high-frequency analog and digital electronic devices. For their technological application, however, carbon nanotubes have to be separated, placed, contacted, and gated in a controlled way. So far, there are no scalable methods or processes known that allow for producing high-performance carbon nanotube transistors with technologically relevant performance and yields.
Usually, two approaches have been proposed for fabricating carbon nanotube field-effect transistors. In the first approach, the carbon nanotubes are grown or dispersed globally on a substrate. In this case, there is only limited control of either the electronic type of the carbon nanotubes or of their density and orientation. While the first approach allows easy formation of carbon nanotubes, the lack of alignment among carbon nanotubes introduces difficulty when integration with semiconductor technology is attempted because current semiconductor manufacturing processes rely on lithographic alignment to enable large scale integration.
In the second approach, carbon nanotubes are placed locally in the device by either chemical or electrical means. These processes involve chemical treatment, transfer, heating, and bending of carbon nanotubes which all result in a deterioration of the transistor performance. The greater the degree of structural and/or chemical damage to the carbon nanotubes, the greater the degradation in the performance of field effect transistors in the second approach.
Another important issue in the design of high-speed carbon nanotube devices has been the limited choice of gate metals and gate dielectric materials and thickness that is critical in view of scaling and integration. Yet another issue is the lack of scalability in the currently available processes for handling carbon nanotubes in order to provide a smaller and faster carbon nanotube device.
In view of the above, there exists a need to provide a process for aligning carbon nanotubes in a manner that is compatible with currently available semiconductor manufacturing processes, is scalable to devices having smaller dimensions, and prevents structural or chemical damages so that performance of the carbon nanotube transistor can be maximized.